Hypergraph partitioning for Electronic Design Automation

Over the last few decades, circuit partitioning has been an area of intense scientific interest. Nowaday, multiple thesis dissertations and articles tackle this topic, which is an important step in Very Large Scale Integration (VLSI). This optimization problem is called by many names, including netlist partitioning, hypergraph partitioning, circuit partitioning, and red-black hypergraph partitioning.

There are different sets of circuits for benchmarking each approach and multiple data types to represent them. Data types are generally associated with a partitioning tool. For example, for hypergraphs partitionner, we have the hgr extensions used by hmetis, khmetis and kahypar, hygr used by patoh and k-patoh, and the format for topopart software.

The aim of this website is to provide references of works about partitioning for Multi-FPGA Systems (MFS). A second topic concerns the elaboration of a public set of circuits for benchmarking each partitioning algorithm. A results section will be updated in order to share current best partitions.